1. Field of the Invention
This invention relates to the testing of CML apparatus and methods, and, more particularly, to a testing apparatus and method which utilizes a power splitter.
2. Description of the Prior Art
It is desirable to fully characterize the propagation delays and transition times of integrated current mode logic (CML) integrated circuits. For relatively small scale integrated circuits a direct probing method was utilized. Specific input and output pins of the CML circuit were connected through printed circuit boards to an oscilloscope and pulse generator. This apparatus and method for characterizing the circuits was effective but as the complexity and higher pin density of large scale integrated circuits the need for another method of characterizing the devices became apparent.
The basic CML circuit has a constant current source applied to the emitters of two transistors. The base of one transistor is connected to a reference voltage and the base of the other transistor is connected to the input signal which is designed to actuate the switching circuit. The collectors of both transistors are tied through resistors to ground. The output of the basic CML switching circuit can be considered to be at either of the collectors of the two transistors. The voltage present on the output of the collector having the reference voltage applied thereto is considered to be the true output and the collector voltage of the other transistor is considered to be the complement. This basic circuit can be utilized to construct the various digital circuits known in the art. For example, it can be utilized to construct AND gates, OR gates, registers, etc.
In order to properly design digital systems it is necessary that the propagation delays and the transition times along with other characteristics of the integrated circuit be known to the designer. Therefore, testing of the CML integrated circuits is necessary. As set forth above the original technique utilized was to directly probe the integrated circuit. With the advent of large scale integrated circuits this became impractical due to the number of pins on the integrated circuit and the number of basic switching circuits present on the CML integrated circuit. The prior constructions of CML testing apparatus do not show the utilization of a power splitter and relay matrix.